m6mgb/t64bm17awg - p renesas lsis 67,108,864 - bit (4,194,304 - word by 16 - bit) cmos flash memory & 16,777,216 - bit (1,048,576 - word by 16 - bit) cmos mobileram stacked - csp ( chip scale package) rev.1.0.48a_bezb 1 the m6mgb/t64bm17awg - p is a stacked chip scale package (s - csp) that contents 64m - bit flash memory and 16m - bit mobileram in a 67 - pin stacked csp with leaded solder ball. 64m - bit flash memory is a 4,194,304 words, single power supply and high performance non - volatile memory fabricated by cmos technology for the peripheral circuit and dinor iv (divided bit - line nor iv) architecture for the memory cell. all memory blocks are locked and can not be programmed or erased, when f - wp# is low. using software lock release function, program or erase operation can be executed. 16m - bit mobileram is a 1,048,576 words high density ram fabricated by cmos technology for the peripheral circuit and dram cell for the memory array. the interface is compatible to an asynchronous sram. the cells are automatically refreshed and the refresh control is not required for system. the device also has the partial block refresh scheme and the power down mode by writing the command. the m6mgb/t64bm17awg - p is suitable for a high performance cellular phone and a mobile pc that are required to be small mounting area, weight and small power dissipation. access time flash 70ns (max.) mobileram 85ns (max.) supply voltage f - vcc=m - vcc=2.7 ~ 3.0v ambient temperature ta= - 40 ~ 85 degree package 67pin s - csp, ball pitch 0.80mm outer - ball: sn - pb application mobile communication products m - gnd : gnd for mobileram a0 - a19 :common address for flash/ mobileram dq0 - dq15 :data i/o f - a20,f - a21 :common address for flash f - ce# :flash chip enable m - ce# : mobileram chip enable m - vcc :vcc for mobileram m - we# :write enable for mobileram f - wp # :write protect for flash m - lb# :lower byte control for mobileram f - rp # :reset power down for flash m - ub # :upper byte control for mobileram f - oe# :output enable for flash memory description features f - vcc :vcc for flash memory f - gnd : gnd for flash memory m - oe# :output enable for mobileram f - we# :write enable for flash memory f - ry/by# : flash memory ready /busy nc : non connection pin configuration (top view) 10.8 mm nc dq15 f - ry/by# nc f - gnd f - vcc m - vcc m - ce# f - oe# f - gnd f - ce# nc m - we# nc nc nc nc nc dq1 dq3 dq5 dq7 dq14 dq4 dq2 dq0 a1 a0 a2 a3 a6 dq8 dq9 dq11 dq10 dq12 dq6 dq13 a9 a14 a13 a12 m - oe# f - rp# a4 a7 a10 a15 a5 nc a8 a11 nc nc f - we# m - gnd f - wp# m - lb# nc nc ( top view) 1 2 3 4 5 6 7 8 a b c d e f g h j k l m 8.5 mm a18 a17 a16 a19 f - a21 m - ub# index(laser marking) f - a20
m6mgb/t64bm17awg - p renesas lsis 67,108,864 - bit (4,194,304 - word by 16 - bit) cmos flash memory & 16,777,216 - bit (1,048,576 - word by 16 - bit) cmos mobileram stacked - csp ( chip scale package) rev.1.0.48a_bezb 2 mcp block diagram note: in the data sheet there are ? vcc ? s , ? gnd ? s , ? oe ? s and ? we ? s. in the flash memory part they mean f - vcc , f - gnd, f - oe and f - we. in the mobileram part they mean m - vcc , m - gnd, m - oe and m - we. in the mobileram part ub# and lb# are m - ub# and m - ub#, respectively. capacitance a0 to a21 a0 to a21 a0 to a19 f - ce# f - wp# f - rp# m - we# m - oe# m - ub# m - lb# m - ce# dq0 to dq15 64 mbit dinor iv flash memory 16 mbit mobileram f - vcc f - gnd m - vcc m - gnd f - oe# f - we# f - oe# f - ry/by# min. typ. max. cin input capacitance a21-a0, f-oe#, f-we#, f-ce#, f-wp#, f- rp#, m-ce#, m-oe#, m-we#, m-lb#, m-ub# 18 pf cout output capacitance dq15-dq0, f-ry/by# 22 pf symbol conditions ta=25c, f=1mhz, vin=vout=0v unit limits parameter
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